Job Title: Senior Verification Engineer
Location : Austin, TX
Ready to sponsor H1B visa
Our client is a Series D semiconductor innovator pioneering programmable coherent DSP (Digital Signal Processing) solutions that power next-generation cloud and AI infrastructure. Their cutting-edge technology enables faster, more efficient data transmission within and between AI data centers - forming a key foundation for the future of AI-driven connectivity.
The company recently emerged from stealth with $180 million in funding, backed by leading investors including Kleiner Perkins, Spark Capital, Mayfield, and Fidelity Investments.
Role Overview:
As a Senior Verification Engineer, you'll play a pivotal role in validating complex digital design blocks and ensuring top-tier performance and reliability of our client's semiconductor solutions. You'll collaborate closely with design engineers and contribute to verification strategy, environment development, and coverage closure.
Key Responsibilities:
Plan and execute verification of digital design blocks per design specifications, collaborating closely with design engineers.
Develop verification environments using SystemVerilog and UVM.
Identify, implement, and track comprehensive coverage measures to validate corner cases.
Debug functionality issues in partnership with design teams.
Perform coverage analysis and drive closure based on defined metrics.
Requirements:
10+ years of industry experience, with 7+ years specifically in verification.
Deep knowledge of VLSI verification flows, methodologies, and concepts.
Proven experience completing 2 or more full block/system verification cycles.
Expertise in SystemVerilog, UVM, Specman, or SystemC.
Experience with data path or data protocols (especially Ethernet) is preferred.
Hands-on experience with verification methodologies such as UVM, OVM, or eRM.
Nice to Have:
Demonstrated success in developing full coverage metrics for complex verification scenarios.
Experience verifying analog/mixed-signal designs in collaborative team environments.
Strong written and verbal communication skills - including the ability to craft test plans, present results, and coordinate across cross-functional teams.
Must have current recent experience as a Verification Engineer
Job stability is mandatory - no job hoppers accepted
Candidates with breaks will not be accepted
Performed at least 2 or more full block/system verification cycles.
In depth knowledge in VLSI verification flow, languages and concepts.
functional block/cluster testing
10+ years of experience; At least 7 years of experience in verification a must.
In depth knowledge in VLSI verification flow, languages and concepts a must.
Deep experience in building verification environments using SystemVerilog and UVM or
specman or systemC
Performed at last 2 or more full block/system verification cycles.
Experience in data path or data protocols, specifically Ethernet - preferred
Verification using one of the known methodologies (eRM, UVM, OVM).
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On-site in Austin, TX, five days a week
Compensation & Benefits:
Equity: Meaningful ownership in a high-growth company
Benefits: Full Medical, Dental, and Vision coverage
Visa Sponsorship: H1-B sponsorship available
Location: On-site in Austin, TX (5 days/week) - this is a must
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